Transfer Learning for Human & AI

This article describes the first public implementation and evaluation of the latest version of the RISC-V hypervisor extension (H-extension v0.6.1)specification in a Rocket chip core . To perform a meaningful evaluation formodern multi-core embedded and mixedcriticality systems, we have ported Bao, anopen-source static partitioning hypervisor, to Risc-V . We have also extended the platformlevel interrupt controller to enable direct guestinterrupt injection with low and deterministic latency . Experiments were carried out in FireSim, a cycle-accurate, FPGA-accelerated simulator .

Author(s) : Bruno Sá, José Martins, Sandro Pinto

Links : PDF - Abstract

Code :


Keywords : risc - core - evaluation - systems - hypervisor -

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