Automatic algorithm-hardware co-design for DNN has shown great success in improving the performance of DNNs on FPGAs . The solution searched by our algorithm achieves 72.5% top-1 accuracy on ImageNet at framerate 50, which is 60% faster than MnasNet . With lowcomputational cost, our algorithm can generate quantized networks that achievestate-of-the-art accuracy and hardware performance on Xilinx Zynq (ZU3EG) FPGA for image classification on image classification . Withlow cost, the algorithm can . achieve . low cost, with low computational cost, it can . . achieve high accuracy and . hardware performance with high hardware performance . with comparable accuracy .

Author(s) : Zhen Dong, Yizhao Gao, Qijing Huang, John Wawrzynek, Hayden K. H. So, Kurt Keutzer

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Keywords : hardware - algorithm - cost - performance - accuracy -

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